When working with the Universal Verification Methodology (UVM) in SystemVerilog, controlling verbosity is essential to manage how much information is displayed during simulation. UVM verbosity determines the amount of detail printed to the console or log file, making debugging and test analysis more efficient. By using the UVM verbosity command line, verification engineers can dynamically adjust the verbosity level without recompiling or modifying source code. This flexibility helps in analyzing simulation results and identifying issues more effectively, especially in complex verification environments.
Understanding UVM Verbosity Levels
In UVM, verbosity refers to the granularity of messages printed during simulation. UVM provides several predefined verbosity levels that control how much diagnostic information is displayed. Each message in UVM is tagged with a verbosity level, and only those messages equal to or lower than the current verbosity threshold are shown.
The predefined verbosity levels in UVM, listed from least to most detailed, are
- UVM_NONE (0)No messages are printed.
- UVM_LOW (100)Minimal, high-level messages are printed.
- UVM_MEDIUM (200)Moderate detail; typically used during normal debugging.
- UVM_HIGH (300)Detailed information useful for deep analysis.
- UVM_FULL (400)Extensive detail, including repetitive or lower-priority messages.
- UVM_DEBUG (500)Maximum verbosity, used for deep internal debugging.
These levels are numeric constants, allowing easy comparison and control. By default, most UVM components start with theUVM_MEDIUMverbosity level, but this can be overridden either programmatically or through command line arguments.
Why Use the Command Line to Set UVM Verbosity
Using the command line to control verbosity is a convenient way to change message behavior without editing source files. In a large verification environment, different users or test cases might require different verbosity settings. Instead of recompiling the testbench each time, engineers can simply use simulation options to modify verbosity dynamically.
This method also helps automate regression runs. You can set different verbosity levels for different runs, allowing detailed logging only when failures occur. It provides a flexible and powerful way to manage output, especially when simulations produce thousands of messages per second.
How to Set UVM Verbosity Using the Command Line
To set verbosity from the command line, the UVM framework provides a special plus argument syntax that works across simulators like VCS, Questa, or Xcelium. The most common format is
+UVM_VERBOSITY=level
Here,levelcorresponds to one of the UVM verbosity constants. For example
+UVM_VERBOSITY=UVM_LOW+UVM_VERBOSITY=UVM_HIGH+UVM_VERBOSITY=UVM_DEBUG
This command globally sets the verbosity for all components in the testbench. It’s particularly useful when running simulations with different levels of detail depending on the debugging stage. However, UVM also allows more fine-grained control over specific components or hierarchies.
Setting Verbosity for Specific Components
Sometimes, increasing verbosity for the entire testbench generates too much output, making it hard to find relevant information. In such cases, UVM allows you to control verbosity at the component level. This is done using the+uvm_set_verbositycommand line argument, which provides a structured way to specify where and how verbosity is applied.
The general syntax is
+uvm_set_verbosity=component_path,verbosity_level,verbosity_value
Each part of the argument serves a specific purpose
- component_pathThe hierarchical path of the component whose verbosity you want to change (e.g.,
env.agent.driver). - verbosity_levelThe verbosity threshold such as
UVM_LOW,UVM_MEDIUM, orUVM_HIGH. - verbosity_valueThe numeric value corresponding to the verbosity level (e.g., 100 for LOW, 200 for MEDIUM).
For example, the following command increases verbosity for the driver component only
+uvm_set_verbosity=uvm_test_top.env.agent.driver,UVM_HIGH,300
This allows detailed logging for the driver while keeping other parts of the environment at their default verbosity levels. It is especially useful when debugging specific modules without overwhelming the output with unnecessary information.
Using Multiple Verbosity Commands
It is possible to use multiple+uvm_set_verbositycommands in the same simulation run to control different components simultaneously. For instance
+uvm_set_verbosity=uvm_test_top.env.agent.monitor,UVM_HIGH,300 +uvm_set_verbosity=uvm_test_top.env.scoreboard,UVM_DEBUG,500
In this example, the monitor prints detailed messages, while the scoreboard displays full debugging information. This targeted approach helps narrow down issues within complex verification systems without flooding the console.
Dynamic Control During Simulation
While the command line is a powerful way to initialize verbosity, UVM also allows changing verbosity dynamically during runtime using built-in methods. The most common one isset_report_verbosity_level_hier(), which can be called from within your test or sequence.
For example
uvm_top.set_report_verbosity_level_hier(UVM_HIGH);
This changes the verbosity level for all components under theuvm_tophierarchy. The advantage of this approach is that you can control verbosity programmatically during specific phases or conditions in the simulation, offering more precise management than the command line alone.
Tips for Effective Verbosity Management
Managing verbosity efficiently can significantly improve debugging speed and simulation clarity. Here are some practical tips
- Start with
UVM_MEDIUMfor general simulations, then increase toUVM_HIGHorUVM_DEBUGonly when needed. - Use
+uvm_set_verbosityto focus on specific components rather than the entire environment. - In regression testing, set verbosity low to save log space and processing time.
- Combine command-line verbosity with runtime verbosity adjustments for flexible control.
- Document the verbosity settings used for each simulation to maintain reproducibility.
Effective verbosity management ensures that you get just the right amount of information, improving both debugging efficiency and simulation performance.
Common Mistakes When Setting Verbosity
Even though verbosity control is straightforward, a few common mistakes can cause confusion. One frequent issue is mistyping the component path in+uvm_set_verbosity. UVM requires the full hierarchical path, and any mismatch prevents the setting from applying correctly.
Another mistake is setting a very high verbosity level globally. This can lead to massive log files and slow simulations. Always verify that your verbosity level matches your debugging needs. Lastly, avoid mixing numeric verbosity values and symbolic constants incorrectly; simulators may interpret them differently depending on syntax.
Practical Example of Using Command Line Verbosity
Consider a scenario where you are debugging a communication protocol verification environment. You might want detailed logs for the driver and monitor components but only summary logs for the rest. You can achieve this with
+UVM_VERBOSITY=UVM_LOW +uvm_set_verbosity=uvm_test_top.env.agent.driver,UVM_HIGH,300 +uvm_set_verbosity=uvm_test_top.env.agent.monitor,UVM_DEBUG,500
This setup provides a balanced level of detail—only essential messages from most components and deeper logs where needed. The command-line flexibility makes this approach ideal for iterative debugging without modifying code.
Setting UVM verbosity through the command line is one of the most effective ways to control message output during simulation. It gives verification engineers precise control over how much information is displayed, where it is shown, and when it is relevant. By using+UVM_VERBOSITYand+uvm_set_verbosityoptions, you can streamline the debugging process, reduce noise, and focus on specific components. Understanding these verbosity mechanisms is essential for maintaining an efficient, organized, and scalable UVM testbench, especially in complex verification environments where clarity and control make all the difference.